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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) cirrus logic, inc. p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs7410 cd/mp3/wma audio controller features l super on-chip integration for low cost and low count bill of materials l 32-bit risc processor performs audio decode and system management functions l 16-bit dsp for audio special effects l 80 kbytes internal sram, and 256 kbytes internal rom l interfaces to external sdram or edo dram (for shock protection), and to external rom/flash (for custom program storage) l cd serial interface with advanced pattern matching and software error handling l integrated dac functionality l simultaneous 4 channels pcm audio output and iec-958 output. l large number of gpio pins for servo control, key scan, lcd control, etc. l three serial control/status ports l sophisticated clock management and low power consumption l supports iso9660 and multi-session write methods l low power 0.18 micron technology l 100-pin mqfp package l 100-pin lqfp package description the cs7410 is a true system-on-a-chip for the cd- based digital audio market. with a powerful risc pro- cessor, one dsp, integrated audio ds modulator, large internal sram and program rom, and glueless inter- face to popular cd chip sets, the cs7410 is a complete single chip low-power programmable audio decoder. this powerful architecture is easily capable of mp3, wma, and other future audio formats. the cs7410?s flexible architecture and low power consumption make it an ideal low-cost solution for a wide range of player ap- plications. for portable audio systems, the memory interface can be used to add dram or sram for elec- tronic shock protection (esp). a flexible set of interfaces are available for end-user i/o such as a keypad and lcd control for use in mass market cd players, boom boxes, and shelf-top systems. ordering information cs7410-cm 0 to 70 c 100-pin mqfp CS7410-CQ 0 to 70 c 100-pin lqfp audio interface ds modulator pcm out iec-958 x,y data memory cpu / mac instruction cache 80 kb internal sram 256 kb internal rom dram control mini dma rom/sram control flash control memory controller register bank system miscellaneous clock control timers get bits data cache instruction cache cpu mac cd interface pll control fifo external interface 2-wire debug interface 3/4 wire serial programmable i/o pwm out risc-32 dsp-16 jul ?02 ds553pp1
cs7410 2 ds553pp1 table of contents 1. characteristics and specifications ........................................................................ 5 1.1 ac and dc parametric specifications ............................................................................... 5 1.1.1 absolute maximum rating .................................................................................... 5 1.1.2 recommended operating conditions ................................................................... 5 1.1.3 electrical specifications ........................................................................................ 5 1.1.4 dc characteristics ................................................................................................ 7 1.1.4.1 sdram interface .................................................................................. 7 1.1.4.2 serial interface .................................................................................... 11 1.1.4.3 edo dram interface .......................................................................... 12 1.1.4.4 flash / rom interface ...................................................................... 15 1.1.4.5 audio output interface ........................................................................ 17 1.1.4.6 cd interface ........................................................................................ 18 1.1.4.7 miscellaneous timings ........................................................................ 20 2. cs7410 summary ................................................................................................................ 21 2.1 cs7410 typical application ............................................................................................. 21 2.2 cs7410 block summaries .............................................................................................. 21 2.2.1 risc-32 .............................................................................................................. 21 2.2.2 dsp-16 ................................................................................................................ 21 2.2.3 system controls .................................................................................................. 21 2.2.4 memory system .................................................................................................. 22 2.2.5 cd interface ........................................................................................................ 22 2.2.6 audio interface .................................................................................................... 22 2.2.7 external interface ................................................................................................ 22 2.2.8 system functions ................................................................................................ 22 3. functional description ............................................................................................... 23 3.1 risc-32 processor .......................................................................................................... 23 3.2 dsp-16 processor ........................................................................................................... 23 3.3 memory control ............................................................................................................... 23 3.4 cd interface ..................................................................................................................... 23 3.5 system control functions ................................................................................................ 23 3.6 audio output .................................................................................................................... 24 4. pin description ................................................................................................................. 25 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not yet available. ?advance? product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (? cirrus?) believe that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before p lacing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of ord er acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights , trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not exte nd to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techno logies described in this ma- terial and controlled under the ?foreign exchange and foreign trade law? is to be exported or taken out of japan. an export lice nse and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this mater ial is subject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). cirrus products are not designed, authorized, or warrant- ed to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names i n this document may be trade- marks or service marks of their respective owners.
cs7410 ds553pp1 3 4.1 pin identification .............................................................................................................. 25 4.2 miscellaneous pins .......................................................................................................... 30 4.3 serial interface pins ........................................................................................................ 30 4.4 sdram / dram interface ............................................................................................... 31 4.5 rom/nvram interface ................................................................................................... 32 4.6 digital audio output interface .......................................................................................... 33 4.7 ds modulator interface .................................................................................................... 33 4.8 cd interface .................................................................................................................... 34 4.9 general purpose input/output (gpio) ............................................................................ 35 4.10 power and ground ........................................................................................................ 36 5. 100-pin mqfp package specifications (20x14x2.85mm) ....................................... 38 6. 100-pin lqfp package specifications (14x14x1.4mm) ........................................... 39 list of figures figure 1. sdram timing ................................................................................................................ 7 figure 2. sdram load mode ......................................................................................................... 8 figure 3. sdram burst write ......................................................................................................... 9 figure 4. sdram burst read ......................................................................................................... 9 figure 5. sdram refresh ............................................................................................................ 10 figure 6. serial interface timing diagram .................................................................................... 11 figure 7. edo page write timing diagram .................................................................................. 13 figure 8. edo page read timing diagram .................................................................................. 13 figure 9. edo refresh timing diagram ....................................................................................... 14 figure 10. flash/rom read ...................................................................................................... 15 figure 11. flash/rom write ....................................................................................................... 16 figure 12. audio output timing .................................................................................................... 17 figure 13. cd interface timing ..................................................................................................... 18 figure 14. cd interface timing diagrams ..................................................................................... 19 figure 15. miscellaneous timings ................................................................................................. 20 figure 16. cs7410 application ..................................................................................................... 21 figure 17. cs7410 pin identification ............................................................................................. 25 figure 18. 100-pin mqfp package (20x14x2.85mm) .................................................................. 38 figure 19. 100-pin lqfp package (14x14x1.4mm) .................................................................... 39 list of tables table 1. sdram characterization data ......................................................................................... 7 table 2. serial interface characterization data ............................................................................ 11 table 3. edo dram characterization data ................................................................................. 12 table 4. flash/rom read characterization data ...................................................................... 15 table 5. audio output interface symbols and characterization data ........................................... 17 table 6. pin type and direction legend ....................................................................................... 25 table 7. pin assignments ............................................................................................................. 26 table 8. miscellaneous interface pins .......................................................................................... 30 table 9. serial interface pins ........................................................................................................ 30 table 10. sdram interface .......................................................................................................... 31 table 11. edo dram interface .................................................................................................... 31 table 12. rom/nvram interface ................................................................................................. 32 table 13. audio output interface .................................................................................................. 33 table 14. ds output interface ....................................................................................................... 33 table 15. cd interface .................................................................................................................. 34
cs7410 4 ds553pp1 table 16. dedicated general purpose i/o pins ............................................................................ 35 table 17. redefined general purpose pins .................................................................................. 35 table 18. power and ground ........................................................................................................ 36
cs7410 ds553pp1 5 1. characteristics and specifications 1.1 ac and dc parametric specifications (agnd, dgnd=0v, all voltages with respect to 0v) 1.1.1 absolute maximum rating caution: operating beyond these minimum and maximum limits can result in permanent damage to the device. cirrus logic recommends that cs7410 devices operate at the settings described in the next ta- ble. 1.1.2 recommended operating conditions 1.1.3 electrical specifications (ta = 0 to 70 o c) symbol description min. max. unit vdd io power supply voltage on i/o ring -0.5 4.6 volts vdd core power supply voltage on core logic and pll -0.5 2.5 volts v i digital input applied voltage (power applied) -0.5 5.5 volts i i digital input forced current -10 10 ma i o digital output forced current -50 50 ma t sol lead soldering temperature 260 o c t vsol vapor phase soldering temperature 235 o c t stor storage temperature (no power applied) -40 125 o c t amb ambient temperature (power applied) 0 70 o c p tot power consumption 1 w parameter symbol min typ max units supply voltage, io v dd 3.0 3.3 3.6 volts supply voltage, core and pll v dd 1.62 1.8v 1.98 volts ambient temperature (power applied) t amb 0 25 70 o c parameter symbol conditions min typ max units power supply supply current, io i dd normal operating 13 ma supply current, core and pll i dd normal operating 70 ma
cs7410 6 ds553pp1 digital pins input voltage, high v ih 2.0 volts input voltage, low v il 0.8 volts input current i in v in = v dd or v ss -1 +1 m a input pull up/down resistor r i 75 k w output voltage, high v oh @ buffer rating 2.4 volts output voltage, low v ol @ buffer rating 0.4 volts high-z-state leakage i oz v out = v ss or v dd -1 +1 m a parameter symbol conditions min typ max units
cs7410 ds553pp1 7 1.1.4 dc characteristics (ta= 25c; vdd_pll=vdd_core=1.8v10%, vdd_io=3.3v10%) 1.1.4.1 sdram interface symbol description min typ max unit t mper dr_cko period 22 ns t mco output delay from dr_cko active edge 19 ns t mdow m_d[15:0] delay from dr_cko 19 ns t mhw m_d[15:0] valid time after dr_cko 5 ns t msur m_d[15:0] setup to dr_cko 13 ns t mhr m_d[15:0] hold time after dr_cko 0 ns table 1. sdram characterization data dr_cko dr_ras_l dr_cas_l m_a m_d (write) m_we_l t mper t mdow m_d (read) t msur t mhr t mhw t mco figure 1. sdram timing
cs7410 8 ds553pp1 dr_cko dr_ras_l dr_cas_l m_a m_d m_we_l figure 2. sdram load mode
cs7410 ds553pp1 9 dr_cko dr_ras_l dr_cas_l m_a m_d m_we_l d0 adras adcas dn ... d1 figure 3. sdram burst write adras adcas dr_cko dr_ras_l dr_cas_l m_a m_d m_we_l d1 dn ... d2 figure 4. sdram burst read
cs7410 10 ds553pp1 dr_cko dr_ras_l dr_cas_l m_we_l m_a m_d figure 5. sdram refresh
cs7410 ds553pp1 11 1.1.4.2 serial interface symbol description min typ max unit t clk_per clock period 66 ns t dms master-mode data setup 28 ns t dmh master-mode data hold 28 ns t dss slave-mode data setup 15 ns t cms master chip select to clock setup 28 ns t dsh slave mode data hold 0 ns table 2. serial interface characterization data ser2_clk (cpol=0) ser2_clk (cpol=1) ser2_do (master) ser2_di (slave) ser2_cs msb lsb lsb msb t clk_per t dms t dmh t dss t dsh t cms figure 6. serial interface timing diagram
cs7410 12 ds553pp1 1.1.4.3 edo dram interface note:values shown are for minimum internal clock period (11ns) and all programmed wait states enabled. symbol description min typ max unit t ras ras low time 72 ns t rp ras high pulse time 40 ns t rcl ras fall to cas fall 38 ns t cas cas low time 30 ns t cpn cas high time 15 ns t cah cas fall to address row 29 ns t asr address row to ras fall 10 ns t rah ras fall to address column 18 ns t asc second address column (burst) to cas fall 10 ns t aa column address to data setup 35 ns t cac cas fall to data setup 17 ns t csr cas fall to ras fall 19 ns t chr ras fall to cas rise 18 ns t crh cas rise to ras rise 6 ns t wds write data setup to cas fall 12 ns t wdh write data hold to cas fall 29 ns t ws write enable setup to cas fall 13 ns t wh write enable hold to cas fall 20 ns t roe ras fall to oe fall -5 5 ns t oer ras rise to oe rise -5 5 ns t dch read data hold to cas rise 0 ns table 3. edo dram characterization data
cs7410 ds553pp1 13 adras adcas dr_ras_l dr_cas_l m_a m_d m_ap_we data data t asr t rah t rcl t cpn adcas t asc t cah t cas t ras t rp t crh t ws t wh t wds t wdh figure 7. edo page write timing diagram adras adcas dr_ras_l dr_cas_l m_a m_d m_ap_oe data data t asr t rah t rcl t cpn adcas t asc t cah t aa t cac t cas t ras t rp t roe t crh t dch t oer figure 8. edo page read timing diagram
cs7410 14 ds553pp1 dr_ras_l dr_cas_l t csr t chr t ras figure 9. edo refresh timing diagram
cs7410 ds553pp1 15 1.1.4.4 flash / rom interface note:values shown are for minimum internal clock period (11ns) and no programmed wait states. symbol description min typ max unit t cspw ce low period 135 ns t rdd1 ce fall to output enable fall 5 ns t rdd2 ce rise to output enable rise -5 5 ns t ads address setup to ce fall -10 10 ns t das data setup after address 1 28 ns t wrsu all outputs setup before we 95 ns t wrpw we pulse width 170 ns t wrh all outputs hold after we 95 ns table 4. flash/rom read characterization data 1. value shown for 3 programmed wait states. nvm_ce_l m_we_l m_ap_oe m_a m_d t ads t cspw t rdd1 t rdd2 t das figure 10. flash/rom read
cs7410 16 ds553pp1 nvm_ce_l m_ap_oe m_a m_d m_we_l t wrsu t wrh t wrpw figure 11. flash/rom write
cs7410 ds553pp1 17 1.1.4.5 audio output interface symbol description min typ max units t axch pcm_xclk high time (pcm_xclk is input/output) 42 50 % t axcl pcm_xclk low time (pcm_xclk is input/output 42 50 % t axper pcm_xclk period (input/output) 55 ns t aoper pcm_bck period (output) 440 ns t sdmo pcm_bck delay from pcm_xclk output transition 1 5 ns t sdmi pcm_bck delay from pcm_xclk input transition 1 15 ns t lrds pcm_lrck delay from pcm_bck transition 1 5 ns t adsm pcm_d[3:0] delay from pcm_bck transition 1 5 ns table 5. audio output interface symbols and characterization data 1. active clock edge is programmable. timing is referenced from the active edge. pcm_bck(output) pcm_xck(input/output) t sdmi sdmo t axch pcm_bck(output) pcm_do[1:0] (output) pcm_lrck(output) t lrds t adsm t axcl t axper t aoper figure 12. audio output timing
cs7410 18 ds553pp1 1.1.4.6 cd interface note:active edge of cd_bclk is programmable symbol description min typ max units t slri cd_lrck setup to cd_bck active edge 7 ns t sdi cd_data and cd_c2p0 setup to cd_bck active edge 7 ns t hsdi cd_data and cd_c2p0 hold time after cd_bck active edge 3 ns cd_bck(input)* cd_do (input) cd_lrck(input) cd_c2po (input) t slri t sdi t hsdi figure 13. cd interface timing
cs7410 ds553pp1 19 1 5 0 1 c d _ b c k c d _ l r c k d a t a c 2 p 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d 0 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d m s b l s b m s b l s b l o w e r ( l e f t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( r i g h t c h a n n e l ) 3 2 - b i t b c k , m s b f i r s t , r i g h t c h a n n e l l o w , c 2 p 0 l s b f i r s t , d a t a l a t c h t i m i n g h i g h 1 5 0 1 c d _ b c k c d _ l r c k d a t a c 2 p 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d 0 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d m s b l s b m s b l s b u p p e r ( r i g h t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( l e f t c h a n n e l ) 3 2 - b i t b c k , m s b f i r s t , l e f t c h a n n e l l o w , c 2 p 0 m s b f i r s t , d a t a l a t c h t i m i n g l o w 1 5 0 1 c d _ b c k c d _ l r c k d a t a c 2 p 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d 0 m s b l s b l o w e r ( l e f t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( r i g h t c h a n n e l ) 2 4 - b i t b c k , m s b f i r s t , r i g h t c h a n n e l l o w , c 2 p 0 m s b f i r s t , d a t a l a t c h t i m i n g h i g h l e f t c h a n n e l r i g h t c h a n n e l r i g h t c h a n n e l l e f t c h a n n e l l e f t c h a n n e l r i g h t c h a n n e l 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d m s b l s b 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 i n v a l i d m s b u p p e r ( l e f t c h a n n e l ) l e f t c h a n n e l c d _ b c k c d _ l r c k d a t a c 2 p 0 i n v a l i d 0 l s b m s b l o w e r ( l e f t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( r i g h t c h a n n e l ) 2 4 - b i t b c k , l s b f i r s t , r i g h t c h a n n e l l o w , c 2 p 0 m s b f i r s t , d a t a l a t c h t i m i n g l o w l e f t c h a n n e l r i g h t c h a n n e l i n v a l i d l s b m s b i n v a l i d l s b u p p e r ( l e f t c h a n n e l ) l e f t c h a n n e l 0 1 5 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 1 5 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 1 1 0 9 8 7 6 5 4 3 2 1 5 0 1 c d _ b c k c d _ l r c k d a t a 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d 0 m s b l s b 2 4 - b i t b c k , m s b f i r s t , r i g h t c h a n n e l l o w , d a t a l a t c h t i m i n g h i g h ( n o t e : n o c 2 p 0 f o r t h i s f o r m a t ) l e f t c h a n n e l r i g h t c h a n n e l 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 i n v a l i d m s b l s b 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 i n v a l i d m s b l e f t c h a n n e l 1 5 0 1 c d _ b c k c d _ l r c k d a t a c 2 p 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 m s b l s b l o w e r ( l e f t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( r i g h t c h a n n e l ) 1 6 - b i t b c k , m s b f i r s t , l e f t c h a n n e l l o w , c 2 p 0 l s b f i r s t , d a t a l a t c h t i m i n g h i g h l e f t c h a n n e l r i g h t c h a n n e l 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 m s b l s b 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 m s b l s b l o w e r ( l e f t c h a n n e l ) u p p e r ( l e f t c h a n n e l ) l o w e r ( r i g h t c h a n n e l ) u p p e r ( r i g h t c h a n n e l ) l e f t c h a n n e l r i g h t c h a n n e l 1 5 0 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 m s b l s b 1 5 1 4 1 3 m s b figure 14. cd interface timing diagrams
cs7410 20 ds553pp1 1.1.4.7 miscellaneous timings symbol description min typ max unit t xclper 1 xtlclk period 59.05 ns t rstl rst_n low pulse width 1000 ns t gph gpio pw high 50 ns t gpl gpio pw low 50 ns 1. value represents typical application with 16.934 mhz crystal reset-n t gph t gp l t rst l xtlclock gpio xccper t figure 15. miscellaneous timings
cs7410 ds553pp1 21 2. cs7410 summary 2.1 cs7410 typical application figure16 shows an example of a complete audio player using the cs7410. 2.2 cs7410 block summaries 2.2.1 risc-32 ? powerful 32-bit risc processor ? comprehensive development tool support ? big or little endian data formats supported ? 32x32 (64-bit result) mac, 2 cycles / multiply with c support ? 4 kbyte instruction cache, 2 kbyte data cache ? single cycle instructions, runs up to 90 mhz 2.2.2 dsp-16 ? powerful 16-bit dsp processor ? 16-bit fixed point logic, with 36 bit accumula- tor. ? single-cycle throughput, 2-cycle latency multi- ply accumulate, 16-bit simple integer logic ? 512 byte instruction cache, 8 kbyte program visible local memory ? single cycle instructions, runs up to 90 mhz ? dsp mac is pipelined, 1 cycle / multiply 2.2.3 system controls ? includes 32 hardware lockable semaphore reg- isters ? two general-purpose registers for inter-proces- servo dsp/rd channel speakers/headphones (2 or 4 channel) pcm dacs op-amps 4 chan. debug optical driver 2 chan. iec-958 rom/flash (optional) 0-2 mb for new code dram edo/sdram (optional) 0-8 mb for shock protection serial eeprom (optional) keypad matrix lcd controller/ display ir receiver gpio memory interface serial interface digital audio out dac out cd interface cs7410 figure 16. cs7410 application
cs7410 22 ds553pp1 sor communication ? three 32-bit timers for i/o and other uses, with programmable interval rates ? ?getbits? module accelerates peripheral stream parsing ? both hardware and software interrupts on data or debug 2.2.4 memory system ? large internal sram (80 kbyte) and internal program rom (256 kbyte) ? supports both synchronous and edo dram (256 kbytes to 8 mbytes) for esp ? supports one bank of flash and rom (up to 2 mbytes) for nonvolatile storage ? 4-, 8-, or16-bit data bus for dram, 8-bit data bus for rom 2.2.5 cd interface ? glueless interfaces to cd servo chip set, sup- porting all standard cd formats ? includes pattern matching hardware to support fast esp recovery 2.2.6 audio interface ? supports 4 channels pcm, i 2 s connectivity at up to 24 bits ? flexible audio clocking scheme using internal pll and dividers, or external pins ? simultaneous iec-958 output with program- mable channel status and user data ? integrated sigma-delta ( ds ) stereo audio mod- ulator 2.2.7 external interface ? 2-wire serial slave port, used for debug ? 3- or 4-wire synchronous serial master/slave port for external controller or slave peripheral ? separate synchronous serial master port opti- mized for receiving cd sub-codes ? up to 29 programmable bi-directional i/o (gpio) and up to 9 output only (gpo) pins (some multiplexed with other peripherals) ? all pins defined as gpios can be used to re- ceive edge or level detection interrupts. ? pulse-width modulated (pwm) output pin can be used to create simple adc using low-cost comparator (i.e., for battery voltage monitor) 2.2.8 system functions ? internal oscillator uses external crystal, or re- ceives clock (i.e. 16.9 mhz) from cd servo ? internal pll generates any system clock fre- quency, chip can run up to 90 mhz ? includes clock divider and clock shutoff cir- cuits for low power/sleep modes ? advanced 0.18 micron cmos technology, runs off 1.8 v and 3.3 v ? all i/o pins are 3.3 v, with 5 v tolerance ? 100-pin mqfp package ? 100-pin lqfp package
cs7410 ds553pp1 23 3. functional description 3.1 risc-32 processor the cs7410 includes a powerful, proprietary 32- bit risc processor backed by powerful software development tools. the risc-32 has a mac en- gine which performs multiply/accumulate in 2 cy- cles with c support, effectively achieving single cycle throughput. there are other instructions that are designed to help with performing audio decoding. the risc processor coordinates on-chip multi-threaded tasks, as well as supervises system activities such as keypad and front panel display control. 3.2 dsp-16 processor the cs7410 contains a proprietary digital signal processor (dsp) called dsp-16, which is opti- mized for audio and sound applications. in the cs7410, the dsp-16 assists with audio decoding and provides added functions such as surround sound and equalization. the dsp performs 16-bit simple integer operations, and has a 16-bit fixed point logic unit with a 32-bit accumulator. there are 24 general-purpose registers, and eight independent address generation registers, featur- ing: post-increment alu, linear and circular buffer operations, bit reverse alu operations, and dual operand read from memory. the multiply-accumu- lator has single-cycle throughput, with two cycle latency. the dsp is optimized for bit packing and unpacking operations. the interface to main mem- ory is designed for bursting flexible block sizes and skip counts. 3.3 memory control the memory controller performs the arbitration functions for all the other modules in the cs7410, allowing access to internal rom and sram, and to external rom and dram. the memory con- troller services and arbitrates a number of clients and stores their code and/or data within the local memory. this arbitration and scheduling guaran- tees the allocation of sufficient bandwidth to the various clients. an optimal application will use only internal rom and sram for code and data storage, which results in the best timing and lowest power consumption. external dram may be used for runtime code storage or for esp ram. in both of these applica- tions, the data throughput requirement is low, and the memory controller acts as a dma engine to move data between external and internal memory with minimal power consumption. the internal rom contains most of the code required for audio decoding and system functions. additional code can be stored in external rom (managed by the memory controller) or a small se- rial rom (controlled by gpios). the cs7410 also supports code storage in external flash with in- system write capability for customer code updates. future firmware releases will provide a complete solution requiring no external rom. 3.4 cd interface the cd interface receives compressed or uncom- pressed (direct audio) data from the cd servo/read channel chip, performs descrambling and crc checking, and writes the data to an internal fifo. additional c3 error decoding is done in software. the cd interface is compatible with all commonly used cd formats. the cs7410 contains a hardware pattern matching circuit to scan the incoming cd data for a pattern of up to 64 bytes. this circuit is used to assist the electronic shock protection function by quickly lo- cating and matching the incoming data with data stored in the esp ram. 3.5 system control functions the system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. two 32-bit communication registers are available for inter-
cs7410 24 ds553pp1 processor communication, and 32 semaphore reg- isters are used for resource locking. three timers are available for general-purpose functions, as well as more specialized functions, such as watchdog timers and performance monitoring. the large number of general purpose i/os offers flexibility in system configurations. three separate synchronous serial interfaces, conforming to indus- try-standard protocols, are available for a variety of system interface functions. four general purpose software interrupts and twelve hardware interrupts help reduce peripheral overhead and improve ui responsiveness. power-down control of the internal clocks is also possible. an internal pll is used to generate the internal system and memory clocks as well as audio clocks for all supported sample rates. 3.6 audio output decoded audio data is written into an output fifo in 16-, 18-, 20- or 24-bit pcm format. a flexible audio output stage can simultaneously output 4 channels of pcm data to external audio dacs, plus an independent iec-958 encoded output. the iec- 958 output has fully programmable channel status (commercial), and provides a flexible solution to support all iec-958 modes for user data. the audio output circuit contains an auto-mute detect circuit, which can generate internal or external mute con- trols pcm fifo data up to 18 bits can also be output by the on-board sigma-delta stereo modulator. the sigma-delta modulator yields a typical 85 db sig- nal-to-noise ratio with few external components re- quired, resulting in a low-cost, low parts count analog front end. the modulator has a 32x upsam- pling filter, followed by a 32x interpolator, and fi- nally a 5 th -order sigma-delta modulator. the auto-mute circuit also works on the modulator out- put, and there are separate programmable attenua- tors for the modulator output and both pcm outputs.
cs7410 ds553pp1 25 4. pin description 4.1 pin identification figure17 shows the cs7410 pins grouped by function, also showing the number of pins in each group. table6 lists the conventions used to identify the pin type and direction.pin assignments. i: input s: schmitt trigger on input u: pull up resistor o: output o4: output ? 4ma drive t4: high z output ? 4ma drive b: bi-direction b4: bi-direction ? 4ma drive d4: bi-direction with 4ma open drain output table 6. pin type and direction legend figure 17. cs7410 pin identification
cs7410 26 ds553pp1 table7 lists the pin number, pin name, and pin type for the 100-pin cs7410 package. for signal pins, the pin direction after reset is shown. the primary function and pin direction is shown for all signal pins. for some signal pins, a secondary function and direction are also shown. pwr: +2.5v or +3.3v power supply voltage gnd: power supply ground name_n: low active name_l: low active table 6. pin type and direction legend (continued) pin name type reset function #1 dir function #2 dir note 1 pll_gnd gnd pll ground 2 pll_1v8 pwr pll power 3 m_d_15 b4 i dram data[15] b nvmem address[19] o 4 m_d_14 b4 i dram data[14] b nvmem address[18] o 5 m_d_13 b4 i dram data[13] b nvmem address[17] o 6 m_d_12 b4 i dram data[12] b nvmem address[16] o 7 m_d_11 b4 i dram data[11] b nvmem address[15] o 8 m_d_10 b4 i dram data[10] b nvmem address[14] o 9 m_d_9 b4 i dram data[9] b nvmem address[13] o 10 m_d_8 b4 i dram data[8] b nvmem address[12] o 11 m_d_7 b4 i dram data[7] b nvmem data[7] b 12 core_1v8 pwr core power 13 m_d_6 b4 i dram data[6] b nvmem data[6] b 14 core_gnd gnd core ground 15 m_d_5 b4 i dram data[5] b nvmem data[5] b 16 io_3v3 pwr i/o power 17 xtlclk_o o o oscillator out o table 7. pin assignments
cs7410 ds553pp1 27 18 xtlclk_i i i oscillator in i 19 io_gnd gnd i/o ground 20 m_d_4 b4 i dram data[4] b nvmem data[4] b 21 m_d_3 b4 i dram data[3] b nvmem data[3] b 22 m_d_2 b4 i dram data[2] b nvmem data[2] b 23 m_d_1 b4 i dram data[1] b nvmem data[1] b 24 m_d_0 b4 i dram data[0] b nvmem data[0] b 25 m_a_11 b4 i dram address[11] o nvmem address[11] o 1 26 m_a_10 b4 i dram address[10] o nvmem address[10] o 1 27 m_a_9 b4 i dram address[19] o nvmem address[9] o 1 28 m_a_8 b4 i dram address[8] o nvmem address[8] o 1 29 m_a_7 b4 i dram address[7] o nvmem address[7] o 1, 3 30 m_a_6 b4 i dram address[6] o nvmem address[6] o 1, 3 31 m_a_5 b4 i dram address[5] o nvmem address[5] o 1, 3 32 m_a_4 b4 i dram address[4] o nvmem address[4] o 1, 3 33 m_a_3 b4 i dram address[3] o nvmem address[3] o 1, 3 34 m_a_2 t4 i dram address[2] o nvmem address[2] o 3 35 m_a_1 t4 i dram address[1] o nvmem address[1] o 3 36 m_a_0 t4 i dram address[0] o nvmem address[0] o 3 37 dr_ras_l t4 i dram ras_l o 38 core_1v8 pwr core power 39 dr_cas_l t4 i dram cas_l o pin name type reset function #1 dir function #2 dir note table 7. pin assignments (continued)
cs7410 28 ds553pp1 40 core_gnd gnd core ground 41 m_we_l t4 i dram we_l o nvm_we_l 42 io_gnd gnd i/o ground 43 dr_cko t4 i sdram cko o 44 io_3v3 pwr i/o power 45 dr_cke t4 i sdram cke o 46 dr_bs_l b4 i sdram bs_l o nvmem address[20] 1 47 m_ap_oe b4 i sdram ap, edo dram oe_l o nvm_ oe_l 1 48 nvm_ce_l t4 i nvm_ce_l o 49 kp_in_0 b4u i gpio[19] b 50 kp_in_1 b4u i gpio[20] b 51 kp_in_2 b4u i gpio[21] b 52 kp_in_3 b4u i gpio[22] b 53 kp_in_4 b4u i gpio[23] b 54 kp_out_0 b4 i gpio[24] b 55 kp_out_1 b4 i gpio[25] b 56 kp_out_2 b4 i gpio[26] b 57 kp_out_3 b4 i gpio[27] b 58 kp_out_4 b4 i gpio[28] b 59 ir_in b4s i gpio[4] b 60 ser1_clk d4s i debug port clock b 61 ser1_dat d4s i debug port data b 62 ser4_clk b4s i gpio[5] b 63 ser4_dat b4s i gpio[6] b 64 io_gnd gnd i/o ground 65 ser2_clk b4 i serial2 clock b gpio[7] b 66 ser2_di b4 i serial2 data in b gpio[8] b 67 ser2_do b4 i serial2 data out b gpio[9] b pin name type reset function #1 dir function #2 dir note table 7. pin assignments (continued)
cs7410 ds553pp1 29 68 ser2_cs b4 i serial2 chip select b gpio[10] b 69 ser3_clk b4 i serial3 clock o gpio[11] b 70 ser3_do b4 i serial3 data out o gpio[12] b 71 core_1v8 pwr core power 72 ser3_di b4 i serial3 data in i gpio[13] b 73 core_gnd gnd core ground 74 ser3_ss0 b4 i serial3 chip select0 o gpio[14] b 75 io_3v3 pwr i/o power 76 ser3_ss1 b4 i serial3 chip select1 o gpio[15] b 77 servock b4 i servo clock in i gpio[17] b 78 pcm_xck b4 i pcm_xck b 79 pcm_mute b4 i pcm_mute o gpo[4] o 1 80 cd_c2p0 b4 i cd_c2p0 i gpio[16] b 81 cd_bclk is i cd_bclk i 82 cd_lrck i i cd_lrck i 83 cd_data i i cd_data i 84 dac_lp o4 o ds dac left positive out o gpo[5] o 85 dac_ln o4 o ds dac left negative out o gpo[6] o 86 io_gnd gnd i/o ground 87 dac_rp o4 o ds dac right positive out o gpo[7] o 88 dac_3v3 pwr ds dac i/o power 89 dac_rp o4 o ds dac right negative out o gpo[8] o 90 rst_n is i reset_l i 91 test i i manufacturing test i 92 pcm_bck b4 o pcm_bck o gpo[0] o 1 93 pcm_lrck b4 o pcm_lrck o gpo[1] o 1 94 pcm_do_0 b4 o pcm_dout[0] o gpo[2] o 2 95 pcm_do_1 b4 o pcm_dout[1] o gpo[3] o 1 96 iec958_o b4 i iec-958 out o gpio[18] b 97 gpio_0 b4 i gpio[0] b pin name type reset function #1 dir function #2 dir note table 7. pin assignments (continued)
cs7410 30 ds553pp1 1. optional pull up or pull down resistor may be connected to configure internal rom program 2. required external resistor required to select processor boot from internal rom (pull down) or external rom (pull up). 3. drives for a short time after reset, then reverts to high impedance 4.2 miscellaneous pins these pins described in table8 are used for used for basic functions such as clocking, reset and infrared receiver interface. the main system clock can be derived from an external crystal connected between the xtlclk_i and xtlclk_o pins, or can be received from the cd servo chip via the xtlclk_i pin. the cs7410 can accommodate a variety of input frequencies, such as 44.1 khz x 256, x 384, or x 512. 4.3 serial interface pins the cs7410 serial interface pins are described in table9 . cs7410 has three dedicated serial ports, each with different protocols. the 2-wire serial port (ser1) supports industry standard protocols. this port is typ- ically used for debug, with the cs7410 as the slave. the slave chip select address is programmable, and defaults to a 7-bit value of 0x1b. a second serial controller (ser2) supports industry standard 3-wire and 4-wire protocols. in master mode, this interface can control a front panel or a small non-volatile memory. in slave mode, it can operate under control of an external processor, for example, in a combination unit. the third serial port (ser3) is a 5-wire master device optimized for reading cd subcodes from the servo chip, and can also be used a general-purpose serial port. 98 gpio_1 b4 i gpio[1] b pwm_out o 99 gpio_2 b4 i gpio[2] b 100 gpio_3 b4 i gpio[3] b pin name type reset function #1 dir function #2 dir note table 7. pin assignments (continued) pin signal name type description 17 xtlclk_o o crystal output 18 xtlclk_i i crystal input, or oscillator input 90 rst_n i asynchronous reset input, active low 91 test i manufacturing test, tie to ground table 8. miscellaneous interface pins pin signal name type description 60 ser1_clk b debug port serial clock 61 ser1_dat b debug port serial data 65 ser2_clk b clock for 4-wire serial port (output for master mode, input for slave mode) 66 ser2_di i input data for 4-wire serial port 67 ser2_do b output data for 4-wire serial port ? may function as bidi- rectional data in 3-wire mode. table 9. serial interface pins
cs7410 ds553pp1 31 4.4 sdram / dram interface these pins are used to interface the cs7410 with external synchronous or edo drams. data widths of 4 to 16 bits are supported. the cs7410 supports word or block transfers (partial word transfers are not re- quired). table10 gives instructions on how to interface to any particular configuration of sdram. table11 gives pin definitions for interfacing to edo dram. 68 ser2_cs b chip select for 4-wire serial port (output if master, input if slave mode). can also be used as bidirectional ready line. 69 ser3_clk o clock output 70 ser3_do o data output ? up to 32 bits per transfer. 72 ser3_di i data input ? up to 96 bits per transfer. 74 ser3_ss0 o slave select for first peripheral (programmable polarity) 76 ser3_ss1 o slave select for second peripheral (programmable polar- ity) table 9. serial interface pins (continued) pin signal name type description 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 20, 21, 22, 23, 24 dram data[15..0] b memory data bus. 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 dram address[11..0] o memory address bus. connect in order starting with dr_addr[0] to all ram address pins not already connected to dr_bs_l or dr_ap. 37 dr_ras_l o memory row address strobe 39 dr_cas_l o memory column address strobe 41 m_we_l o memory write enable 43 dr_cko o sdram clock 45 dr_cke o sdram clock enable 46 dr_bs_l o bank selection. always connect to ram bs or bs0 pin. 47 m_ap_oe o memory auto pre-charge. always connect to ram ap pin. table 10. sdram interface pin signal name type description 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 20, 21, 22, 23, 24 dram data[15..0] b memory data bus. table 11. edo dram interface
cs7410 32 ds553pp1 4.5 rom/nvram interface the rom/nvram interface pins are described in table12 . this interface connects to the non-volatile memory that contains the firmware. the memory could be rom, nvram (flash), eeprom, or any com- bination of these memory types. this interface can also connect to sram that would emulate a rom on a development system. the bus width is always 8 bits. most of these pins are shared with the dram interface, which operates simultaneously with the rom/nvram interface. a number of pins are defined to accept con- figuration input at power-up (see table7 ), allowing different branches to be taken in the firmware. a config- uration resistor is required on pin pcm_do_0 to select whether the processor will boot from internal or external rom . 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 dram address[11..0] o memory address bus. 37 dr_ras_l o memory row address strobe 39 dr_cas_l o memory column address strobe 41 m_we_l o memory write enable 47 m_ap_oe o memory output enable pin signal name type description table 11. edo dram interface (continued) pin signal name type description 11, 13, 15, 20, 21, 22, 23, 24 nvmem data[7..0] b memory data bus (shared with bits [7:0] of dram data bus). 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 nvm_addr[11..0] o memory address bus[11..0] (shared with dram address bus) 3, 4, 5, 6, 7, 8, 9, 10 nvm_addr[19..12] o memory address bus[19..12] (shared with bits [15..8] of dram data bus). 46 nvm_addr[20] o memory address bus[20] (dram bs_l pin). 41 nvm_we_l o nvram write enable (shared with dram we_l pin) 47 nvm_oe_l o nvram write enable (shared with dram we_l pin) 48 nvm_ce_l o rom/nvram chip enable. table 12. rom/nvram interface
cs7410 ds553pp1 33 4.6 digital audio output interface the digital audio output interface pins are described in table13 . this is the audio pcm interface that con- nects to an audio pcm dac. the sample rate and the size of the samples are programmable to accommo- date any commercially available dac. the cs7410 has two data output pins, for up to 4 channels of pcm output, and a separate output pin to simultaneously output iec-958 encoded data (either compressed or uncompressed). 4.7 ds modulator interface the ds interface pins are described in table14 . the cs7410 contains a stereo delta-sigma ( ds ) modula- tor, which outputs two differential digital signals on four pins. these outputs are design to drive an external op-amp based integrator circuit (contact cirrus logic applications engineering for details) . pin signal name type description 78 pcm_xck b audio 256x/384x/512x clock input or output to serial dac. when output, it?s generated from cs7410 internal pll. 77 servock i optional source of audio 256x/384x/512x audio clock. may be used for cd direct audio to match input and output clocks. 79 pcm_mute o audio mute control to external dac. polarity is programma- ble and is three-stated at power up. 92 pcm_bck o audio bit clock output to serial dac. polarity is programma- ble. 93 pcm_lrck o audio out left/right clock to serial dac. 94 pcm_do_0 o audio serial pcm data out[0]. 95 pcm_do_1 o audio serial pcm data out[1]. 96 iec958_o o iec-958 output table 13. audio output interface pin signal name type description 84 dac_lp o ds left channel, positive output 85 dac_ln o ds left channel, negative output 87 dac_rp o ds right channel, positive output 89 dac_rn o ds right channel, positive output table 14. ds output interface
cs7410 34 ds553pp1 4.8 cd interface the cd interface pins are described in table15 . this interface is used to read serial cd data from a cd servo/read channel chip. the interface supports all standard formats, including 16 mhz, 24 mhz and 32 mhz clocks per container. control of the cd servo chip is done by the risc processor using gpios, and cd subcode data is read using the dedicated serial interface (ser3). pin signal name type description 81 cd_bclk i cd clock input ? polarity is programmable 82 cd_lrck i cd left-right clock input 83 cd_data i cd serial data input 80 cd_c2p0 i cd error signaling input table 15. cd interface
cs7410 ds553pp1 35 4.9 general purpose input/output (gpio) the cs7410 provides a number of general purpose input/output (gpio) pins, each with individual output three-state controls, and a number of general purpose output (gpo) pins. table16 shows the 17 dedicat- ed gpio pins. a naming scheme for these pins was chosen to encourage system designers to adhere to standardized pin usage. table17 shows the gpio and gpo pins that can be redefined from other functions. for redefined pins, mode control register bits select the normal function or gpio/gpo function for the pins. table17 also indicates which mode bit controls each pin. pin signal name type description 100, 99, 98, 97 gpio[3:0] b 4 general purpose i/o on dedicated pins 53, 52, 51, 50, 49 kp_in[4:0] b 5 general purpose i/o on dedicated pins 58, 57, 56, 55, 54 kp_out[4:0] b 5 general purpose i/o on dedicated pins 59 ir_in b general purpose i/o on dedicated pin 62 ser4_clk b general purpose i/o on dedicated pin 63 ser4_dat b general purpose i/o on dedicated pin table 16. dedicated general purpose i/o pins pin signal name type description 65 ser2_clk b gpio controlled by mode bit 2 67 ser2_do b gpio controlled by mode bit 2 68 ser2_cs b gpio controlled by mode bit 2 66 ser2_di b gpio controlled by mode bit 3 69 ser3_clk b gpio controlled by mode bit 4 70 ser3_do b gpio controlled by mode bit 4 72 ser3_di b gpio controlled by mode bit 4 74 ser3_ss0 b gpio controlled by mode bit 4 76 ser3_ss1 b gpio controlled by mode bit 5 80 cd_c2p0 b gpio controlled by mode bit 6 77 servock b gpio controlled by mode bit 7 92 pcm_bck o gpo controlled by mode bit 8 93 pcm_lrck o gpo controlled by mode bit 9 94 pcm_do_0 o gpo controlled by mode bit 10 95 pcm_do_1 o gpo controlled by mode bit 11 79 pcm_mute o gpo controlled by mode bit 12 84 dac_lp o gpo controlled by mode bit 13 table 17. redefined general purpose pins
cs7410 36 ds553pp1 4.10 power and ground table18 describes the power and ground pins. the cs7410 requires 3 different types of power supplies for the plls, internal logic, and io pins. the plls and internal logic use 1.8 v supply voltage. the io pins use 3.3 v supply voltage. an optional separate supply can be used to provide clean 3.3 v to the sigma-delta dacs digital output pads. it is recommended that you use good layout techniques to provide isolation be- tween the supply types on the board. contact cirrus logic applications engineering for layout guidelines. 85 dac_ln o gpo controlled by mode bit 13 87 dac_rp o gpo controlled by mode bit 13 89 dac_rn o gpo controlled by mode bit 13 96 iec958_o b gpio controlled by mode bit 14 pin signal name type description 1 pll_gnd ground for internal plls 2 pll_1v8 1.8v for internal plls 14, 40, 73 core_gnd ground for internal core logic 12, 38, 71 core_1v8 1.8v for internal core logic 19, 42, 64, 86 io_gnd ground for digital i/os 16, 44, 75 io_3v3 3.3v for digital i/os 88 dac_3v3 3.3v for sigma delta dac digital i/os table 18. power and ground pin signal name type description table 17. redefined general purpose pins (continued)
cs7410 ds553pp1 37
cs7410 38 ds553pp1 5. 100-pin mqfp package specifications (20x14x2.85 mm ) 0.310 0.050 a 0.650 0.150 3.300 (max) 1.600 0.150 detail a 0.800 0.150 0~8 0.1500.008 20.000 0.100 23.200 0.250 100 31 50 81 1 14.000 0.100 17.200 0.250 30 51 80 2.85 0.127 0.200 (min) 1.35 0.05 figure 18. 100-pin mqfp package (20x14x2.85mm) note: measurement units = mm
cs7410 ds553pp1 39 6. 100-pin lqfp package specifications (14x14x1.4 mm ) figure 19. 100-pin lqfp package (14x14x1.4mm)

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